Wafer level packaging

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Hermetically sealed and reliable packaging solutions based on glass|Si materials for System-in-package (SiP) and MEMS applications.

Creating a hermetically sealed workspace in which “the heart” of the application can operate under ideal technological conditions, is an ongoing challenge. For example, while some cases need a high vacuum inside the workspace, others might require a specific gas combination.

Packaging on wafer level

Particularly for MEMS applications there is an increased risk of damages if and when unpackaged dies are handled by standard ‘pick-and-place’ processes. Therefore, it is crucial to cover the chips with a robust mechanical package before any dicing and assembling processes start. Whatever the final design of an application – the generic solution to this particular issue is a ‘capping wafer’, based on glass or silicon, or even a combination of materials.

When necessary more functionalities can be integrated into the package.

Project example

The development result is an “impact stopper structure” that is based on the dual-depth cavity principle, composed of two bonded glass wafers. The silicon sensor wafer is encapsulated in two symmetric glass capping wafers. The dual-depth cavities provide enough room for vibration, while the open cavities above the bond pads enable subsequent access for electronic interconnections.

The mainly applied technologies in this project are wet etching, laser machining and wafer bonding on 200 mm glass wafer size.